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mp38876 15a, 28v, high frequency step-down converter with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 1 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. the future of analog ic technology description the mp38876 is a monolithic step-down switch mode converter with a built in internal power mosfet. it achieves 15a continuous output current over a wide input supply range with excellent load and line regulation. current mode operation provides fast transient response and eases loop stabilization. fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. the mp38876 requires a minimum number of readily available standard external components and is available in a 20-pin 3mm x 4mm qfn package. the mp38876 is ideal for a wide range of applications including distributed power systems, pre-regulator for linear regulators, compact dc- dc regulators for pcb space limited platforms. features ? wide 4.5v to 28v operating input range ? 15a output current ? 25m ? internal power mosfet switch ? synchronous gate driver ? synch from 300khz to > 1mhz external clock or 400khz fixed switching frequency ? synch output to drive another regulator in phase-shift operation ? feedback voltage accuracy: 2% ? programmable soft-start ? startup tracking ? en and power good for power sequencing ? cycle-by-cycle over current protection ? thermal shutdown ? output adjustable from 0.8v to 12v ? stable with low esr output ceramic capacitors ? available in a 3mm x 4mm qfn package applications ? distributed power systems ? pre-regulator for linear regulators ? compact dc-dc regulator for pcb space limited platforms ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application mp38876 sw bg fb bst gnd in vcc comp pg en v out 1.2v/15a v in off on v cc r3 c3 m2 c6 system ss/trk syncin syncout efficiency vs. output current v in =12v,v out =1.2v 50 55 60 65 70 75 80 85 90 95 0 2 4 6 8 10 12 14 16 out put current ( a) efficiency (%)
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 2 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. ordering information part number* package top marking free air temperature (t a ) MP38876DL 3mm x 4mm qfn20 38876 ?40 c to +85 c * for tape & reel, add suffix ?z (e.g. MP38876DL?z). for rohs compliant packaging, add suffix ?lf (e.g. MP38876DL?lf?z) package reference top view pin 1 id 1 2 3 4 5 6 7 vcc syncout syncin en ss/trk fb comp 17 16 15 14 13 12 11 sw vin pg bst vin gnd gate vin 8910 20 19 18 absolute maxi mum ratings (1) supply voltage v in ....................................... 30v v sw ....................................... ?0.3v to v in + 0.3v v bs ....................................................... v sw + 6v all other pins .................................?0.3v to +6v continuous power dissipation (t a = +25c) (2) ??????????????????....2.9w junction temperature ...............................150 c lead temperature ....................................260 c storage temperature.............. ?65 c to +150 c recommended operating conditions (3) supply voltage v in ...........................4.5v to 28v output voltage v out .................... 0.8v to v in -4v operating junct. temp (t j )..... ?40 c to +125 c thermal resistance (4) ja jc qfn20 (3mm x 4mm) .............48 ...... 11 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 3 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. electrical characteristics v in = 12v, t a = +25 c, unless otherwise noted. parameters symbol condition min typ max units t a =+25 c 0.798 0.810 0.822 v feedback voltage v fb -40 c t a +85 c 0.794 0.826 v feedback current i fb v fb = 0.8v 10 na switch on resistance (5) r ds(on) 25 m ? switch leakage v en = 0v, v sw = 0v 0.1 10 a current limit (5) 21 a oscillator frequency f sw v fb = 0.6v, sync in = 5v 400 khz fold-back frequency v fb = 0v 100 khz maximum duty cycle v fb = 0.6v 90 % minimum on time (5) t on 100 ns soft-start charging current i ss v ss = 0v 8 a maximum comp level v comp_max v fb = 0.6v 4.4 v gain of error amplifier g ea v comp = 1.5v 2 ma/v error amplifier sink current v comp = 1.5v ?270 a error amplifier source current v comp = 1.5v +270 a power good ramp up threshold 90 % power good ramp down threshold 85 %
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 4 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. electrical characteristics ( continued ) v in = 12v, t a = +25 c, unless otherwise noted. parameters symbol condition min typ max units power good delay 20 s power good sink cu rrent capability v pg sink 4ma 0.4 v power good leakage current i pg_leak v pg = 3.3v 10 na v cc tolerance v cc i cc = 0ma 5.3 v v cc regulation i cc = 0~20ma 5 % sync frequency f sync 0.3 1 mhz syncin bias current i syncin 10 na syncin logic high voltage 2 v syncin logic low voltage 0.4 v synchout high level v cc = 5v, source 5ma 4.6 v synchout low level v cc = 5v, sink 5ma 0.4 v under voltage lockout threshold rising 3.85 4.1 4.35 v under voltage lockout threshold hysteresis 900 mv en input low voltage 0.4 v en input high voltage 2 v v en = 2v 2 en input current v en = 0v 0.1 a supply current (shutdown) v en = 0v 0.1 a supply current (quiescent) v en = 2v, v fb = 1v 1.0 ma thermal shutdown 150 c gate driver sink impedance r sink 1 ? gate driver source impedance r source 4 ? gate drive current sense trip threshold 20 mv t d1 from bg low to sw high 10 ns gate drive non-overlap time (see figure 1) (5) t d2 from sw low to bg high 10 ns . v bg 1v t d1 t d2 1v 1v 1v v sw figure 1?gate drive non-overlap time diagram
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 5 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. pin functions pin # name description 1 vcc bg driver bias supply. decouple with a 1f ceramic capacitor. 2 syncout timing output to drive another mp38876 (or similar device) syncin for phase-shift operation. 3 syncin external frequency sy nchronization. connect to v cc if not used. 4 en on/off control. 5 ss/trk soft-start/track input. connect a capacitor to ground. 6 fb feedback. an external resistor divider fr om the output to gnd, tapped to the fb pin, sets the output voltage. to prevent current limit run away during a short circuit fault condition the frequency foldback comparator lowers the oscillator frequency when the fb voltage is below 400mv. 7 comp compensation. connect r/c network to ground. 8 pg power good indicator. connect this pin to v cc or v out by a 100k ? pull-up resistor. the output of this pin is an open drain if the output voltage is within 10% of the nominal voltage, otherwise it is low. if pg is initially at open drain, there is a 20s delay to pull pg if the output voltage is less than 10% regulation window. 9 bst bootstrap. this capacitor is needed to drive the power switch?s gate above the supply voltage. it is connected between sw and bs pins to form a floating supply across the power switch driver. 10, 18, exposed pad vin supply voltage. the mp38876 operates from a +4.5v to +28v unregulated input. c1 is needed to prevent large voltage spikes from appearing at the input. 11-17 sw switch output. these pins are fused together. 19 gate gate driver output. connect this pin to the synchronous mosfet. 20 gnd ground.
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 6 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. typical performance characteristics v in =12v, v out =1.2v, l=0.72uh, t a = +25oc, unless otherwise noted. efficiency vs. output current load regulation 50 55 60 65 70 75 80 85 90 95 0 2 4 6 8 10 12 14 16 out put current ( a) 0.900 0.910 0.920 0.930 0.940 0.950 0.960 0.970 0.980 0.990 1.000 024681012141618202224 load current(a) normalized output voltage (v) 0.998 0.9985 0.999 0.9995 1 1.0005 1.001 5 6 7 8 9 10 11 12 13 14 15 16 17 input voltage (v) normalized output voltage (v) 11 13 15 17 19 21 23 25 0 10203040506070 duty cycle (%) peak current (a) peak current vs. duty cycle 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 input voltage(v) vcc(v) 4 7 10 13 16 19 22 25 28 31
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 7 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. typical performanc e characteristics ( continued ) v in =12v, v out =1.2v, l=0.72uh, t a = +25oc, unless otherwise noted. output ripple two phase steady state waveform two phase transient response input ripple i out =15a i out =30a i out =15a input voltage(v) case temperature vs. output current enabled supply current vs. input voltage i out =0a i_inductor 10a/div i_inductor 10a/div i_inductor 10a/div i_inductor 5a/div i_inductor 10a/div i out =0a i out =1a - 20a output short circuit i_inductor 10a/div 8 18 28 38 48 58 68 78 88 345678910111213141516 output current(a) vsw 10v/div vsw 10v/div vsw 10v/div v o 1v/div v o/ac 50mv/div v o/ac 50mv/div v in/ac 50mv/div vsw 10v/div vsw 10v/div disabled supply current vs. input voltage i out =0a input voltage(v) i out _max(a) v out (v) 5 7 9 11 13 15 17 19 21 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 975 1005 1035 1065 1095 1125 1155 1185 1215 5 9 13 17 21 25 29 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 4 7 10 13 16 19 22 25 28 31 v in =5v, 400khz v in =12v, 400khz v in =19v, 400khz
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 8 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. function block diagram in en fb sw vcc bg gnd pg bst regulator oscillator 400khz driver current sense amplifier error amplifier current limit comparator pwm comparator d regulator reference -- + -- + -- + s r r q q -- + comp power good v fb v bg ss/trk i ss v cc syncout syncin v cc v bc v fb driver figure 2?functional block diagram operation the mp38876 is a fixed frequency, synchronous, step-down switching regulator with an integrated high-side power mosfet and a gate driver for a low-side external mosfet. it achieves 15a continuous output current over a wide input supply range with excellent load and line regulation. it provides a single highly efficient solution with current mode control for fast loop response and easy compensation. the mp38876 operates in a fixed frequency, peak current control mode to regulate the output voltage. a pwm cycle is initiated by the internal clock. the integrated high-side power mosfet is turned on and remains on until its current reaches the value set by the comp voltage. when the power switch is off, it remains off until the next clock cycle starts. if, in 90% of one pwm period, the current in the power mosfet does not reach the comp set current value, the power mosfet will be forced to turn off. error amplifier the error amplifier compares the fb pin voltage with the internal 0.8v reference (ref) and outputs a current proportional to the difference between the two. this output current is then used to charge or discharge the external compensation network to form the comp voltage, which is used to control the power mosfet current. the optimized external compensation network minimizes the external component counts and simplifies the control loop design. see application information for compensation network design.
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 9 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. internal regulator most of the internal circuitries are powered from the 5v internal regulator. this regulator takes the vin input and operates in the full vin range. when vin is greater than 5.0v, the output of the regulator is in full regulation. when vin is lower than 5.0v, the output decreases. since this internal regulator provides the bias current for the bottom gate driver that requires significant amount of current depending upon the external mosfet selection, a 1f ceramic capacitor for decoupling purpose is required. under-voltage lockout (uvlo) under-voltage lockout (uvlo) is implemented to protect the chip from operating at insufficient supply voltage. the mp38876 uvlo comparator monitors the output voltage of the internal regulator, vcc. the uvlo rising threshold is about 4.0v while its falling threshold is a consistent 3.2v. soft-start the soft-start is implemented to prevent the converter output voltage from overshooting during startup. when the chip starts, the internal current source (10a) charges up an external soft start capacitor c ss from 0v t o 1.2v. when it is lower than the internal reference (ref), ss overrides ref so the error amplifier uses ss as the reference. when ss is higher than ref, ref regains control. over-current-protection and latch off the mp38876 has cycle-by-cycle over current limit. if the soft start voltage is greater than 1.2v, and inductor current exceeds the current limit threshold, and fb voltage drops below 50% of reference voltage, then the mp38876 goes into latch off until en or in is recycled. this protection mode is especially useful when the output is dead-short to ground. thermal shutdown thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. when the silicon die temperature is higher than 150 c, it shuts down the whole chip. when the temperature is lower than its lower threshold, typically 140 c, the chip is enabled again. floating driver and bootstrap charging the floating power mosfet driver is powered by an external bootstrap capacitor. this floating driver has its own uvlo protection. this uvlo?s rising threshold is 2.2v with a hysteresis of 150mv. the bootstrap capacitor voltage is regulated internally by v in through d1, m3, c4, l1 and c2 (figure 3). if (v in -v sw ) is more than 5v, u2 will regulate m3 to maintain a 5v bst voltage across c4. -- + -- + v in 5v u2 d1 m3 bst sw c4 c2 l1 v out figure 3 ? internal bootstrap charging circuit startup and shutdown if both vin and en are higher than their appropriate thresholds, the chip starts. the reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. the regulator provides stable supply for the remaining circuitries. three events can shut down the chip: en low, vin low and thermal shutdown. in the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. the comp voltage and the internal supply rail are then pulled down. the floating driver is not subject to this shutdown command. synchin/synchout control the mp38876 has a dedicated synchin control pin (syncin) that allows mp38876 be synchronized to external clock ranging from 300khz up to 1 mhz. the mp38876 also has a synchout pin (syncout) generating a 50% duty cycle, 180 out of phase logic signal. the synchout signal can be used to synchronize a slave phase by connecting the syncout pin of the master mp38876 with the syncin pin of the slave mp38876. the 180 interleaving operation greatly reduces the requirement of the input decoupling capacitors.
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 10 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. application information setting the output voltage the external resistor divider is used to set the output voltage (see the typical application circuit on the front page). the feedback resistor r1 also sets the feedback loop bandwidth with the internal compensation capacitor (see figure 1). choose r1 to be around 40.2k ? for optimal transient response. r2 is then given by: 1 v 8 . 0 v 1 r 2 r out ? = table 1?resistor selection for common output voltages v out (v) r1 (k ? ) r2 (k ? ) 1.2 40.2 (1%) 40.4 (1%) 1.8 40.2 (1%) 32.4 (1%) 2.5 40.2 (1%) 19.1 (1%) 3.3 40.2 (1%) 13 (1%) 5 40.2 (1%) 7.68 (1%) selecting the inductor a 1h to 10h inductor with a dc current rating of at least 25% percent higher than the maximum load current is recommended for most applications. for highest efficiency, the inductor dc resistance should be less than 7m ? . for most designs, the inductance value can be derived from the following equation. osc l in out in out f i v ) v v ( v l ? = where i l is the inductor ripple current. choose inductor current to be approximately 30% of the maximum load current, 15a. the maximum inductor peak current is: 2 i i i l load ) max ( l + = under light load conditions below 200ma, larger inductance is recommended for improved efficiency synchronous mosfet the external synchronous mosfet is used to supply current to the inductor when the internal high-side switch is off. it reduces the power loss significantly when compared against a schottky rectifier. table 2 lists example synchronous mosfets and manufacturers. table 2?synchronous mosfetselection guide manufacture part no. siliconix si7336adp ir 1rfh7932p6f input capacitor the input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the ac current to the step-down converter while maintaining the dc input voltage. use low esr capacitors for the best performance. ceramic capacitors are preferred, but tantalum or low-esr electrolytic capacitors may also suffice. since the input capacitor (c1) absorbs the input switching current it requires an adequate ripple current rating. the rms current in the input capacitor can be estimated by: ? ? ? ? ? ? ? ? ? = in out in out load 1 c v v 1 v v i i the worst case condition occurs at v in = 2v out , where: 2 i i load 1 c = for simplification, choose the input capacitor whose rms current rating greater than half of the maximum load current. the input capacitor can be electrolytic, tantalum or ceramic. when using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1 f, should be placed as close to the ic as possible. when using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. the input voltage ripple caused by capacitance can be estimated by: ? ? ? ? ? ? ? ? ? = in out in out s load in v v 1 v v 1 c f i v output capacitor the output capacitor (c2) is required to maintain the dc output voltage. ceramic,
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 11 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. tantalum, or low esr electrolytic capacitors are recommended. low esr capacitors are preferred to keep the output voltage ripple low. the output voltage ripple can be estimated by: ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? = 2 c f 8 1 r v v 1 l f v v s esr in out s out out where l is the inductor value and resr is the equivalent series resistance (esr) value of the output capacitor. in the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. the output voltage ripple is mainly caused by the capacitance. for simplification, the output voltage ripple can be estimated by: ? ? ? ? ? ? ? ? ? = in out 2 s out out v v 1 2 c l f 8 v v in the case of tantalum or electrolytic capacitors, the esr dominates the impedance at the switching frequency. for simplification, the output ripple can be approximated to: esr in out s out out r v v 1 l f v v ? ? ? ? ? ? ? ? ? = the characteristics of the output capacitor also affect the stability of the regulation system. the mp38876 can be optimized for a wide range of capacitance and esr values. compensation components mp38876 employs current mode control for easy compensation and fast transient response. the system stability and transient response are controlled through the comp pin. comp pin is the output of the internal error amplifier. a series capacitor-resistor combination sets a pole-zero combination to control the characteristics of the control system. the dc gain of the voltage feedback loop is given by: out fb vea cs load vdc v v a g r a = where avea is the error amplifier voltage gain, 9600v/v; g cs is the current sense transconductance, 12.8a/v; rload is the load resistor value. the system has two poles of importance. one is due to the compensation capacitor (c3), the output resistor of error amplifier. the other is due to the output capacitor and the load resistor. these poles are located at: vea ea 1 p a 3 c 2 g f = load 2 p r 2 c 2 1 f = where, g ea is the error amplifier transconductance, 2.4ma/v. the system has one zero of importance, due to the compensation capacitor (c3) and the compensation resistor (r3). this zero is located at: 3 r 3 c 2 1 f 1 z = the system may have another zero of importance, if the output capacitor has a large capacitance and/or a high esr value. the zero, due to the esr and capacitance of the output capacitor, is located at: esr esr r 2 c 2 1 f = in this case (as shown in figure 3), a third pole set by the compensation capacitor (c6) and the compensation resistor (r3) is used to compensate the effect of the esr zero on the loop gain. this pole is located at: 3 r 6 c 2 1 f 3 p = the goal of compensation design is to shape the converter transfer function to get a desired loop gain. the system crossover frequency where the feedback loop has the unity gain is important. lower crossover frequencies result in slower line and load transient responses, while higher crossover frequencies could cause system unstable. a good rule of thumb is to set the crossover frequency to approximately one- tenth of the switching frequency. the table 3 lists the typical values of compensation components for some standard output voltages with various output capacitors and inductors. the values of the compensation components have been optimized for fast transient.
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 12 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. table 3?compensation values for typical output voltage / capacitor v out (v) l1 (h) c2, ceramic (f) c2, poscap (f)/esr(m ? ) r3 (k ? ) c3 (nf) c6 (pf) 1.2 0.82 100x2 none 2.2 10 100 1.2 0.82 47 330/ 9/ 6.3v 5.49 3.3 560 1.8 0.82 47 330/ 9/ 6.3v 8.25 2.2 390 2.5 1.2 47 330/ 9/ 6.3v 11.5 1.5 270 3.3 1.3 47 220/ 18/ 6.3v 8.06 2.7 680 5 1.8 47 220/ 18/ 6.3v 16 1 100 to optimize the compensation components the following procedure can be used. 1. choose the compensation resistor (r3) to set the desired crossover frequency. determine the r3 value by the following equation: fb out cs ea c v v g g f 2 c 2 3 r = where f c is the desired crossover frequency. 2. choose the compensation capacitor (c3) to achieve the desired phase margin. for applications with typical inductor values, setting the compensation zero, f z1 , below one forth of the crossover frequency provides sufficient phase margin. determine the c3 value by the following equation: c f 3 r 2 4 3 c > 3. determine if the second compensation capacitor (c6) is required. it is required if the esr zero of the output capacitor is located at less than half of the switching frequency, or the following relationship is valid: 2 f r 2 c 2 1 s esr < if this is the case, then add the second compensation capacitor (c6) to set the pole fp3 at the location of the esr zero. determine the c6 value by the equation: 3 r r 2 c 6 c esr = pcb layout guide pcb layout is very important to achieve stable operation. please follow these guidelines and take figure 4 for references. 1) keep the path of switching current short and minimize the loop area formed by input cap, high-side and low-side mosfets. 2) keep the connection of low-side mosfet between sw pin and input power ground as short and wide as possible. 3) ensure all feedback connections are short and direct. place the feedback resistors and compensation components as close to the chip as possible. 4) route sw away from sensitive analog areas such as fb. 5) connect in, sw, and especially gnd respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. top layer
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 13 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. bottom layer figure 4?pcb layout external bootstrap diode an external bootstrap diode may enhance the efficiency of the regulator. the applicable conditions of external bst diode are: z v out =5v or 3.3v; and z duty cycle is high: d= in out v v >65% in these cases, an external bst diode is recommended from the output of the voltage regulator to bst pin, as shown in figure.5 mp38876 sw bst c l bst c 5v or 3.3v out external bst diode in4148 + figure 5?add optional external bootstrap diode to enhance efficiency the recommended external bst diode is in4148, and the bst cap is 0.1~1f. output voltage tracking and sequencing the mp38876 allows the user to program how its output voltage ramps during startup by means of the ss pin. through this pin, the output voltage can be set to either coincidentally or rationally track another output voltage, as shown below. output voltage mp38876 fb sw ss l 1 r 1 r 1 r 2 v out2 r 2 v out2 v out2 v out1 v out1 c out1 v out1 mp38876 fb sw ss l 2 r 3 r 4 r 2 = r 4 (a) coincidentally tracking (a) rationally tracking r 3 > r 1 c out2 v out2 mp38876 fb sw ss l 1 r 1 r 2 c out1 v out1 mp38876 fb sw ss l 2 r 3 r 4 r 2 = r 4 r 3 > r 1 c out2 v out2 figure 6?output voltage tracking
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver mp38876 rev. 0.91 www.monolithicpower.com 14 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. two phase operation the mp38876 can be configured as a two-phase interleaving regulator to provide up to 30a load current. the current balance is automatically achieved by connecting the two comp pins together. see figure 7 for detail configurations. mp38876 mp38876 r14 100k r5 6.8k r10 51 r13 51 r1 6.19k r2 12.7k r4 10 r8 100k r3 100k vin track c12 470uf c1 22uf c2 22uf c5 0.1uf c10 47uf 6.3v c11 330uf 2v c7 2.2nf c8 150pf c6 150pf c4 1uf c3 0.1uf c9 10nf pg gnd vout + + en u1 gnd fb comp bg sw pg bst sw sw sw sw sw sw syncin syncout css/trk vin vin vcc l1 0.72uh/35a m1 si7336a n-ch 30v 27a we-744325072 17 4 1 10 18 319 7 9 8 6 20 2 5 16 15 14 13 12 11 c5a 0.1uf c10a 47uf 6.3v c3a 0.1uf r19 10 m2 si7336a n-ch 30v 27a l2 0.72uh / 35a we-744325072 c11a 330uf 2v c2a 22uf c1a 22uf c4a 0.1uf vin vin vcc u2 en syncin syncout css/trk gnd fb comp bg sw bst pg sw sw sw sw sw sw 18 8 9 17 16 15 14 13 12 11 19 7 6 10 1 4 3 2 5 20 + figure 7?two phase operation
mp38876 ? 15a, 28v, high frequency st ep-down with synchronous gate driver notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp38876 rev. 0.91 www.monolithicpower.com 15 11/4/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. package information qfn20 (3mm x 4mm) side view top view 1 20 10 7 bottom view 2.90 3.10 3.90 4.10 2.40 2.60 0.50 bsc 0.18 0.30 0.80 1.00 0.00 0.05 0.20 ref pin 1 id marking 0.50 0.50 0.25 recommended land pattern 1.10 note: 1) all dimensions are in millimeters. 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeter max. 4) jedec reference is mo-220, variation vged. 5) drawing is not to scale. pin 1 id see detail a 2.50 0.70 pin 1 id option b r0.20 typ. pin 1 id option a 0.20x45 o typ. detail a 0.30 0.50 pin 1 id index area 0.65 0.85 0.65 0.85 18 8 3.90 0.75 0.75 0.50 bsc 0.18 0.30 3.00 bsc 0.25 ref 11 17 0.55 0.50 0.25

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